Self-Aligned-Gate InGaAs HEMTs with Record High-Frequency Characteristics

We have developed a new self-aligned gate technology for InGaAs High Electron Mobility Transistors with non-alloyed Mo-based ohmic contacts and a very low parasitic capacitance gate design. The new process delivers a contact resistance of 7 Ohm-μm and a source resistance of 147 Ohm-μm. The nonalloyed Mo-based ohmic contacts show excellent thermal stability up to 600 °C. Using this technology, we have demonstrated a 60 nm gate length self-aligned InGaAs HEMT with gm = 2.1 mS/μm at VDS = 0.5 V, and fT = 580 GHz and fmax = 675 GHz at VDS = 0.6 V. These are all record or near record values for this gate length. Introduction Reducing source and drain parasitic resistance is essential to boosting the frequency response of III-V High Electron Mobility Transistors (HEMTs) [1-2]. A key to accomplishing this is to shrink the source-gate contact separation, LGS. Stateof-the-art III-V HEMTs typically feature LGS values in the range of 0.5 to 1 μm which result in source resistance (Rs) in InGaAs HEMTs of around 200 ohm-μm. The lowest source resistance in InGaAs HEMTs has been reported by Matsuzaki [3] as Rs = 100 Ohm-μm in non-self-aligned devices with a gate-source separation, LGS = 100 nm. To improve beyond this, a self-aligned gate design is essential. Several self-alignment schemes for InGaAs HEMTs have been demonstrated in the literature [4-5]. In one approach, after T-shape gate formation, ohmic metal is deposited using the gate as a mask. This results in LGS of about half the gate head size [4]. In a separate approach demonstrated by our group, W was used as non-alloyed ohmic contacts with the gate nested inside an opening in a self aligned way. Through this technology 90 nm gate length InGaAs HEMTs were demonstrated with LGS = 60 nm [5]. This technology featured a simple lift-off gate with high parasitic capacitance. As a result, the frequency response of the fabricated transistors was unremarkable. In this work, we demonstrate a new self-aligned gate technology with non-alloyed Mo-based ohmic contacts and a very low parasitic capacitance gate design. The new process delivers very low values of contact resistance and source resistance and record high-frequency characteristics. The proposed device architecture allows for the incorporation of a high-K gate dielectric in the gate stack to achieve MOS type devices. Process Technology Fig. 1 shows a simplified process sequence on a HEMT heterostructure. Device fabrication starts with blank 20 nm Mo e-beam evaporation after removal of the native oxide in an HCl based solution. This Mo layer serves as source and drain nonalloyed ohmic contact. The process follows with mesa isolation, Ti/Mo ohmic pad, SiO2 sacrificial layer deposition and Ti/Au contact pad formation. The first step in T-shape gate formation is a double-exposure double-development gate resist process (Fig. 1a). This is followed by etching of an opening in the SiO2 by anisotropic CF4/H2/Ar based plasma (Fig. 1b). We then carry out isotropic etching of the Mo layer by CF4/O2 plasma (Fig. 1c) to place the edge of the Mo contacts at a controlled distance away from the edges of the gate (set by the edge of the SiO2 sacrificial layer). Following this, we perform a two-step gate recess process which consists of cap removal by a citric acid based solution followed by Ar based plasma for the InP etch stop (Fig. 1d). This results in a slight undercut of the Mo contact layer. We then evaporate and lift off a Pt/Ti/Pt/Au gate stack followed by a thermal step to drive the Pt into the InAlAs barrier and achieve an effective barrier thickness of tins = 5 nm. Devices with Lg in the range of 50 to 150 nm were fabricated. Fig. 2 shows a schematic cross section of the final device. Fig. 3 shows STEM images of a fabricated Lg = 60 nm device. The gate to source contact separation (LGS) and siderecess-length (Lside) were 100 nm and 200 nm, respectively. Fig. 1 Process flow for SAG structure: a) double exposure and double development e-beam process, b) CF4/H2/Ar based plasma etching to create opening in SiO2, c) CF4/O2 plasma to isotropically etch Mo, and d) two-step gate recess process using Citric acid and Ar plasma to expose barrier. 30.7.1 IEDM10-696 978-1-4244-7419-6/10/$26.00 ©2010 IEEE For our first device demonstration, we used a metamorphic InAlAs/InGaAs heterostructure grown on a GaAs substrate with dual Si-doping layers which are located in the upper InAlAs barrier to enhance electron tunneling at the contacts. The channel is made out of In0.7Ga0.3As and is 10 nm thick. DC and Microwave Characteristics Fig. 4 shows resistance measurements in TLM structures. We compare our approach using Mo blanket deposition and dry etching with a scheme based on standard Mo evaporation plus lift-off. Also, as reference, we add earlier self-aligned Wbased ohmic results [5]. The new Mo-based approach yields an Rc of 7 Ohm-μm. This is nearly an order of magnitude improvement over previous self-aligned ohmic-contact technology [5] and a record value among non-alloyed ohmic contacts to InGaAs FETs. Also, blanket Mo deposition yields better results than a Mo lift-off process due to the absence of residual photoresist at the metal-semiconductor interface. Our Mo contact technology is also thermally stable up to 600C. Fig. 5 shows output characteristics of a typical Mo-based SAG HEMT with Lg = 50 nm. The device exhibits excellent saturating characteristics with low RON and a high current of 0.68 mA/μm at VDS = 0.5 and VGS-VT = 0.33 V (2/3 of VDS). Fig. 6 shows typical current and transconductance characteristics vs. VGS at VDS = 0.5 V. This device exhibits over 2.2 mS/μm of maximum transconductance, a record value for Lg = 50 nm HEMTs at VDS = 0.5 V. This result arises from the reduced source resistance of the SAG structure. Fig. 7 shows subthreshold characteristics for VDS = 50 mV and 0.5 V. The subthreshold swing S = 120 mV/dec and DIBL = 160 mV/V that we obtain are not as good as earlier demonstrations from our group. This is the consequence of slightly higher gate leakage current. An optimized heterostructure and Pt sinking process should correct this. Fig. 2 Final cross section of Mo-based SAG HEMT. Fig. 3 Cross-section STEM images of Mo-based SAG HEMT with Lg = 60 nm with 100 nm gate-source contact separation and Lside=200 nm. The barrier thickness, tins, is estimated to be 5 nm. Fig. 4 TLM measurements for three different contact schemes. The gap length in each contact was measured by SEM. 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.0 0.2 0.4 0.6 0.8 1.0 0 V 0.1 V 0.2 V 0.3 V 0.4 V